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| ir3823 1 www.irf.com ? 2012 international rectifier august 1, 2013 3a highly integrated sup ir buck ? single-input v olta g e, s y nchronous buck re g ulato r features description ? single input voltage range from 5v to 21v ? wide input voltage range from 1.0v to 21v with external v cc bias voltage ? output voltage from 0.6v to 0.86% of pvin ? enhanced line/load regulation with feedforward ? programmable switching frequency up to 1.5mhz ? three user selectable soft-start time options ? thermally compensated current limit with robust hiccup mode over current protection ? synchronization to an external clock ? precise reference voltage (0.6v+/-0.6%) ? open-drain pgood indication ? output over voltage protection ? enable input with under-voltage lockout (uvlo) ? v cc under-voltage lockout (uvlo) ? enhanced pre-bias start-up ? integrated mosfet drivers and bootstrap diode ? thermal shut-down ? -40c to 125c operating junction temperature ? 3.5mm x 3.5mm pqfn package ? lead-free, halogen-free and rohs6 compliant the ir3823 supirbuck ? is a 3a easy-to-use, fully integrated and highly efficient synchronous buck regulator intended for point-of-load (pol) applications. the ir3823 features programmable switching frequency from 300khz to 1.5mhz, three selectable soft-start time options, and smooth synchronization to an external clock. the ir3823 uses voltage mode control employing a proprietary pwm modulator, allowing high control bandwidth and fast loop response with less output capacitors. the other important functions include thermally compensated over current protection, output over voltage protection and thermal shut-down, etc. the ir3823 is offered in a small 3.5mm x 3.5mm pqfn package with excellent thermal performance. ? applications ? computing applications ? set top box applications ? storage applications ? data center applications ? telecom applications ? distributed point of load power architectures ordering information base part number package type standard pack orderable part number form quantity ir3823 pqfn 3.5 mm x 3.5 mm tape and reel 750 ir3823mtr1pbf ir3823 pqfn 3.5 mm x 3.5 mm tape and reel 4000 ir3823mtrpbf ??????? ?????? ir3823 ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? pbf ? lead free tr/tr1 ? tape and reel m ? pqfn package
ir3823 2 www.irf.com ? 2012 international rectifier august 1, 2013 basic application figure 1: ir3823 basic application circuit figure 2: ir3823 efficien cy pinout diagram 12 11 10 16 123456 7 8 9 fb s s _select comp gnd rt / sync pgoo d vin vcc/ldo_out gnd pgnd pvin gnd boot gnd enable 13 14 15 sw ir3823 figure 3: 3.5mm x 3.5mm pqfn (top view) ir3823 3 www.irf.com ? 2012 international rectifier august 1, 2013 block diagram fb rt/sync sw pgnd enable vcc oc tsd hdin uvcc uven hdrv ldrv vin ssok 0.6v vref seq por por uvcc gnd oc ov ov vin ss_select fb vcc/ ldo_out 5.1v internal ldo uvcc thermal shut down fault control + - + e/a c omp vref + - control logic 0.15v soft start uven por over voltage fault por vref intl_ss por gate drive pvin ldin boot vcc por fault over ? current ? protection pgood figure 4: simplified block diagram ir3823 4 www.irf.com ? 2012 international rectifier august 1, 2013 pin descriptions pin # pin name pin description 1 fb inverting input to the error amplifier. this pi n is connected directly to the output of the regulator via resistor divider to set the out put voltage and provide feedback to the error amplifier. 2 ss_select soft start selection pin. three user select able soft start time is available: 1.5ms (ss_select=vcc), 3ms (ss_select =float), 6ms (ss_select=gnd) 3 comp output of the error amplifier. the lo op compensation network should be connected between comp and fb pin. 4,9,13, 16 gnd analog ground for the intern al reference and the control circuitry. 5 rt/sync multi-function pin to set the switching frequen cy. the internal oscillator frequency is set with a resistor between this pin and gnd. or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 pgood open-drain power good indication pin. conn ect a pull-up resistor from this pin to vcc. 7 vin input of the internal ldo. a 1.0fceramic c apacitor should be connected between this pin and pgnd. if an external vcc voltage is used, this pin should be shorted to vcc pin. 8 vcc/ldo_out output of the internal ldo and optional inpu t of an external biased supply voltage. a minimum 2.2f ceramic capacitor is recommended between this pin and pgnd. 10 pgnd power ground. this pin serves as a separ ated ground for the mosfet drivers and should be connected to the system power ground plane. 11 sw switch node. connect this pin to the output inductor. 12 pvin power stage input. 14 boot supply voltage for the high-side driver. a 100nf ceramic capacitor should be connected between this pin and sw pin. 15 enable enable pin to turn on/off the device. connect th is pin to pvin pin through a resistor divider to implement the input voltage uvlo. ir3823 5 www.irf.com ? 2012 international rectifier august 1, 2013 absolute maximum ratings stresses beyond these listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any ot her conditions beyond those indicated in the operational sections of the specifications are not implied. pvin, vin to pgnd (note 3) -0.3v to 25v vcc/ldo_out to pgnd (note 3) -0.3v to 8v (note 1) boot to pgnd (note 3) -0.3v to 33v sw to pgnd (note 3) -0.3v to 25v (dc), -4v to 25v (ac, 100ns) boot to sw -0.3v to v cc + 0.3v (note 2) pgood, ss_select to gnd (note 3) -0.3v to v cc + 0.3v (note 2) other input/output pins to gnd (note 3) -0.3v to +3.9v pgnd to gnd -0.3v to +0.3v thermal information junction to ambient thermal resistance ? ja 37.4 c/w (note 4) junction to pcb thermal resistance ? j-pcb 10.1 c/w junction to case top thermal resistance ? j-ctop 120 c/w storage temperature range -55c to 150c junction temperature range -40c to 150c note ? 1: ? vcc ? must ? not ? exceed ? 7.5v ? for ? junction ? temperature ? between ?\ 10c ? and ?\ 40c ? note ? 2: ? must ? not ? exceed ? 8v ?? note ? 3: ? pgnd ? pin ? and ? gnd ? pin ? are ? connected ? together. ?????? note ? 4: ?? ja ? is ? for ? the ? test ? in ? still ? air ? with ? irdc3823 ? evaluation ? board. ? the ? irdc3823 ? uses ? a ? 4 \ layer ? 2.6? ? x ? 2.2? ? fr4 ? pcb ? board. ? each ? layer ? uses ? 2 ??? oz. ? copper. ?????? ? ir3823 6 www.irf.com ? 2012 international rectifier august 1, 2013 electrical specifications recommended operating conditions symbol min max units input voltage range with external vcc (note 5, note 7) pv in 1.0 21 v input voltage range with internal ldo (note 6, note 7) v in , pv in 5.5 21 supply voltage range (note 6) v cc 4.5 7.5 supply voltage range (note 6) boot to sw 4.5 7.5 output voltage range v 0 0.6 0.86 x pv in output current range i 0 0 3 a switching frequency f s 300 1500 khz operating junction temperature t j -40 125 c ? note ? 5: ? v in ? is ? connected ? to ? v cc ? to ? bypass ? the ? internal ? ldo. ?? note ? 6: ? v in ? is ? connected ? to ? pv in . ? for ? single \ rail ? applications ? with ? pv in =v in = ? 4.5v \ 5.5v, ? please ? refer ? to ? the ? application ? information ? in ? the ??? section ? of ? internal ? ldo ? and ? the ? section ? of ? over ? current ? protection. ?? note ? 7: ? maximum ? sw ? node ? voltage ? should ? not ? exceed ? 25v. ?? electrical characteristics unless otherwise specified, these s pecifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ss_select=float. typical values are specified at t a = 25c. parameter symbol conditions min typ max units power stage power losses p loss pv in = v in = 12v, v o = 1.2v, i o = 3a, f s = 1000khz, l = 1.0uh, note 8 0.6 w top switch r ds(on) r ds(on)-t v boot -vsw=5.1v,i o = 3a, t j = 25c 40 52 m ? bottom switch r ds(on) r ds(on)-b v cc = 5.1v, i o = 3a, t j = 25c 26 34 bootstrap diode forward voltage v d i(boot) = 10ma 180 260 470 mv sw leakage current i sw v sw = 0v, enable = 0v, v fb =1v 1 a v sw = 0v, enable = high, v fb =1v 1 a dead band time t d note 8 12.5 ns supply current vin supply current (standby) i in(standby) en = low, no switching v in =21v, pv in =0v 200 a vin supply current (dynamic) i in(dyn) en = high, f sw =1000khz, v in = pv in = 16v 10 12.5 ma ir3823 7 www.irf.com ? 2012 international rectifier august 1, 2013 electrical characteristics (continued) unless otherwise specified, these s pecifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ss_select=float. typical values are specified at t a = 25c. parameter symbol conditions min typ max units v cc /ldo_out output voltage v cc v in (min) = 5.5v, i o = 0-25ma c load = 2.2uf 4.75 5.1 5.4 v ldo dropout voltage v cc_drop v in =4.7v, i o =15ma, c load =2.2uf 0.4 v short circuit current i short v in =7.3v, pv in =float, v cc =0v 70 ma oscillator rt voltage v rt 1.0 v frequency range f s rt = 80.6k ? 270 300 330 khz rt = 23.2k ? 900 1000 1100 rt = 15k ? 1350 1500 1650 ramp amplitude v ramp v in = 5.5v, vin slew rate max = 1v/s, note 8 0.825 v p-p v in = 12v, vin slew rate max = 1v/s, note 8 1.80 v in = 21v, vin slew rate max = 1v/s, note 8 3.15 v in =v cc =5v, for external v cc operation, note 8 0.75 ramp offset note 8 0.16 v minimum pulse width t min(ctrl) note 8 60 ns maximum duty cycle d max f s = 300khz, v in =pv in = 12v 86 % fixed off time t off note 8 200 250 ns sync frequency range f sync 270 1650 khz sync pulse duration t sync 100 200 ns sync level threshold high 3.0 v low 0.6 v error amplifier input bias current (v fb ) i fb (e/a) -1 +1 a output sink current i sink (e/a) 0.4 0.85 1.2 ma output source current i source (e/a) 4 7.5 11 ma slew rate sr note 8 7 12 20 v/s gain-bandwidth product gbwp note 8 20 30 40 mhz ir3823 8 www.irf.com ? 2012 international rectifier august 1, 2013 electrical characteristics (continued) unless otherwise specified, these s pecifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ss_select=float. typical values are specified at t a = 25c. parameter symbol conditions min typ max units error amplifier (continued) dc gain gain note 8 100 110 120 db maximum output voltage v max (e/a) 1.7 2.0 2.3 v minimum output voltage v min (e/a) 100 mv reference voltage (v ref ) ? feedback voltage v fb 0.6 v accuracy 0c < t j < 70c -0.6 +0.6 % -40c < t j < 125c ; note 9 -1.2 +1.2 soft start soft start ramp rate ss_select=v cc 0.34 0.4 0.46 mv/s ss_select=float 0.16 0.2 0.24 ss_select=gnd 0.085 0.1 0.115 ss_select input bias current ss_select=gnd 40 80 ua power good power good turn on threshold vpg (on) v fb rising 85 90 95 % v ref power good lower turn off threshold vpg (lower) v fb falling 80 85 90 % v ref power good turn on delay tpg (on)_d v fb rising, see vpg (on) 2.56 ms power good upper turn off threshold vpg (upper) v fb rising 115 120 125 % v ref pgood comparator delay v fb < vpg (lower) or v fb > vpg (upper) 1 2 3.5 s pgood voltage low pg(voltage) i pgood = -5ma 0.5 v under-voltage lockout v cc -start threshold v cc uvlo start v cc rising trip level 3.9 4.1 4.3 v v cc -stop threshold v cc uvlo stop vcc falling trip level 3.6 3.8 4.0 v enable-start-threshold enable uvlo start ramping up 1.14 1.2 1.26 v enable-stop-threshold enable uvlo stop ramping down 0.95 1 1.05 enable leakage current i en_lk enable = 3.3v 1 a ir3823 9 www.irf.com ? 2012 international rectifier august 1, 2013 electrical characteristics (continued) unless otherwise specified, these s pecifications apply over, 5.5v < v in = pv in < 21v, 0c < t j < 125c, ss_select=float. typical values are specified at t a = 25c. parameter symbol conditions min typ max units over-voltage protection ovp trip threshold ovp_v th v fb rising 115 120 125 % v ref ovp comparator delay t ovp_d 1 2 3.5 s over-current protection current limit i limit t j = 25c, v cc =5.1v 3.6 4.5 5.4 a hiccup blanking time t blk_hiccup ss_select = vcc, note 8 10 ms ss_select = float, note 8 20 ss_select = gnd, note 8 40 over-temperature protection thermal shutdown threshold note 8 145 c hysteresis note 8 20 note ? 8: ? guaranteed ? by ? design, ? but ? not ? tested ? in ? production. ? note ? 9: ? cold ? temperature ? performance ? is ? guaranteed ? via ? correlation ? using ? statistical ? quality ? control. ? not ? tested ? in ? production. ? ir3823 10 www.irf.com ? 2012 international rectifier august 1, 2013 typical efficiency and power loss curves ? pv in = v in =12v, v cc = internal ldo, i o = 0a-3a, room temperature, no air flow . note that the efficiency and power loss curves include the losses of ir3823, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the out put voltages in the efficiency measurement. vout (v) f s (khz) lout (h) p/n dcr (m ? ) size (mm) 1.0 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 pimb053t-1r2ms-39 (cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 xal5030-222me (coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 xal5030-222me (coilcraft) 13.2 5.28x5.48x3.1 ir3823 11 www.irf.com ? 2012 international rectifier august 1, 2013 typical efficiency and power loss curves ? pv in = 12v, v in =v cc = external 5v, i o = 0a-3a, f s = 1000 khz, room temperature, no ai r flow. note that the efficiency and power loss curves include the losses of ir3823, the inductor lo sses and the losses of the inpu t and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. vout (v) f s (khz) lout (h) p/n dcr (m ? ) size (mm) 1.0 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 pimb053t-1r2ms-39 (cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 xal5030-222me (coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 xal5030-222me (coilcraft) 13.2 5.28x5.48x3.1 ir3823 12 www.irf.com ? 2012 international rectifier august 1, 2013 typical efficiency and power loss curves ? pv in = v in = v cc = 5v, i o = 0a-3a, f s = 1000 khz, room temperature, no air flow . note that the efficiency and power loss curves include the losses of ir3823, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the out put voltages in the efficiency measurement. vout (v) f s (khz) lout (h) p/n dcr (m ? ) size (mm) 1.0 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 3.3 1000 1.0 XFL4020-102ME (coilcraft) 10.8 4.0x4.0x2.1 ir3823 13 www.irf.com ? 2012 international rectifier august 1, 2013 r ds(on) of mosfets over temperature at v cc =5.1v ir3823 14 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating character istics (-40c to +125c) ??????? ?????????? ? ? ? ??????? ? ? ? ?????? ? ? ir3823 15 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating character istics (-40c to +125c) ? ? ?????? ? ? ? ? ?????? ? ? ? ? ??????? ? ir3823 16 www.irf.com ? 2012 international rectifier august 1, 2013 theory of operation description the ir3823 supirbuck ? is a 3a easy-to-use, fully integrated and highly efficient synchronous buck regulator intended for point-of-load (pol) applications. it includes two ir hexfets with low r ds(on ). the bottom fet has an integrated monolithic schottky diode in place of a conventional body diode. the ir3823 provides precisely regulated output voltage programmed via two external resistors from 0.6v to 0.86v in . it uses voltage mode control employing a proprietary pwm modulator with input voltage feedforward. that provides excellent noise immunity, easy loop compensation design, and good line transient response. the ir3823 has an internal low dropout (ldo) regulator, allowing single supply operation without resorting to an external bias supply voltage. to further improve the light load efficiency, the internal ldo can be bypassed by using an external bias supply. this mode allows the input bus voltage range extended down to 1.0v. the ir3823 features programmable switching frequency from 300khz to 1.5mhz, three selectable soft-start time, and smooth synchronization to an external clock. the other important functions include thermally compensated ov er current protection, output over voltage protection, pre-bias start-up, enable with input voltage monitoring, pgood output and thermal shut-down. voltage loop com pesnation design the ir3823 uses pwm voltage mode control. the output voltage of the pol, sensed by a resistor divider, is fed into an internal error amplifier (e/a). the output of the e/r is then compared to an internal ramp voltage to determine the pulse width of the gate signal for the control fet. the amplitude of the ramp voltage is proportional to v in so that the bandwidth of the voltage loop remains almost constant for different input voltages. this feature is called input voltage feedfoward. it allows the feedback loop design independent of the input voltage. please refer to the next section for more information. a rc network has to be connected between the fb pin and the comp pin to form a feedback compensator. the goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45 or above. the high control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors, the pcb size and the cost. a phase margin of 45 or higher is desired to ensure the syst em stability. for most applications, a gain margin of -10db or higher is preferred to accommodate component variations and to eliminate jittering/noise. the proprietary pwm modulator in ir3823 significantly reduces the pwm jittering, allowing the control bandwidth in the range of 1/10 th to 1/5 th of the switching frequency. two types of compensators are commonly used: type ii (pi) and type iii (pid ), as shown in figure 5. the selection of the compensation type is dependent on the esr of the output capacitors. electrolytic capacitors have relatively higher esr. if the esr pole is located at the frequency lower than the cross-over frequency, f c , the esr pole will help to boost the phase margin. thus a type ii compensator can be used. for the output capacitors with lower esr such as ceramic capacitors, type iii compensation is often desired. (a) (b) figure 5: loop compensator (a) type ii, (b) type iii ir3823 17 www.irf.com ? 2012 international rectifier august 1, 2013 table 1 lists the compensation selection for different types of output capacitors. for more detailed design guideline of voltage loop compensation, please refer to the application note an-1162, ? compensation design procedure for buck converter with voltage-mode error-amplifier ?. supbuck design tool is also available at www.irf.com providing the reference design based on user?s design requirements. t able 1 r ecommended compensation type compensator location of cross-over frequency type of output capacitors type ii (pi) f lc ir3823 18 www.irf.com ? 2012 international rectifier august 1, 2013 the enable pin should not be left floating. a pull- down resistor in the range of several kilo ohms is recommended to connect between the enable pin and gnd. in addition to logical inputs, the enable pin can be used to implement precise input voltage uvlo. as shown in figure 7, the input of the enable pin is derived from the pv in voltage by a set of resistive divider, r1 and r2. by selecting different divider ratios, users can program the uvlo threshold voltage. the bus voltage uvlo is a very desirable feature. it prevents the ir 3823 from regulating at pv in lower than the desired voltage level. figure 8 shows the start-up waveform with the input uvlo voltage set at 10v. figure 7: implementation of input under-voltage lockout (uvlo) using enable pin ? figure 8: illustration of start-up with pvin uvlo threshold voltage of 10v. the internal soft-start is used in this case. internal low dropout regulator the ir3823 has an internal low dropout regulator (ldo), offering a v cc voltage of 5.1v. the internal ldo is beneficial for single rail (supply) applications, where no external bias supplies will be needed. for these applications, v in pin should be connected to pv in and v cc /ldo_out pin is left floating as shown in figure 9. 1.0 f and 2.2 f ceramic bypass capacitors should be placed close to v in pin and v cc /ldo_out pin respectively. ? figure 9: internally biased single-rail configuration when vin drops below 5.5v, the internal ldo enters the dropout mode. figure 10 shows the v cc /ldo_out voltage for v in =pv in =5v with switching frequency of 600khz and 1500khz respectively. alternatively, if the input bus voltage, pv in , is in the range of 4.5v to 7.5v, v cc /ldo_out pin can be directly connected to pv in pin to bypass the internal ldo and therefore to avoid the voltage drop on the internal ldo. this configuration is illustrated in figure 11. figure 12 shows the configur ation using an external v cc voltage. with this configuration, the input voltage range can be extended down to 1.0v. please note that the input feedforward function is disabled for this configuration. the feedback compensation needs to be adjusted accordingly. it should be noted as the v cc voltage decreases, the efficiency and the over cu rrent limit will decrease due to the increase of r ds(on) . please refer to the section of the over current protection for more information. ir3823 19 www.irf.com ? 2012 international rectifier august 1, 2013 figure 10: ldo dropout voltage at v in =pv in =5v ? figure 11: single-rail configuration for 4.5v-7v inputs figure 12: use external bias voltage . soft-start the ir3823 has an internal digital soft-start circuit to control the output voltage rise time, and to limit the current surge at the start-up. to ensure correct start- up, the soft-start sequence initiates when the enable and vcc voltages rise above their uvlo thresholds and generate the power on ready (por) signal. the slew rate of the internal soft-start can be adjusted externally with ss_select pin, as shown in table 2. table 2 user selectable soft-start time ss_select slew rate (mv/ s) soft-start time ( ms ) vcc 0.4 1.5 float 0.2 3 gnd 0.1 6 figure 13 shows the waveforms during soft start. the corresponding soft-start time can be calculated as follows. slewrate v v t ss 15 . 0 75 . 0 ? ? por intl_ss vout 0.15v 0.75v t 1 t 2 t 3 1.5v 3.0v ? figure 13: theoretical start-up waveforms using internal soft-start it should be noted that during the soft-start, the over- current protection (ocp) and over-voltage protection (ovp) is enabled to protect the device for any short circuit or over voltage condition. pre-bias start-up ir3823 is able to start up into a pre-charged output smoothly, which prevents oscillations and disturbances of t he output voltage. ir3823 20 www.irf.com ? 2012 international rectifier august 1, 2013 the output starts in an asynchronous fashion and keeps the synchronous mosfet (sync fet) off until the first gate signal for control mosfet (ctrl fet) is generated. figure 14 shows a typical pre- bias condition at start up. the gate signal of the control fet is determined by the loop compensator. the sync fet always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state val ue. the number of these startup pulses for each step is 16 and it?s internally programmed. figure 15 show s the series of 16x8 startup pulses. it should be noted that during pre-bias start up, pgood is not active until the first gate signal for control fet is generated. please refer to power good section for more information. ? figure 14: pre-bias start-up ... ... ... hdrv ... ... ... 16 end of pb ldrv 12.5% 25% 87.5% 16 ... ... ... ... ? figure 15: pre-bias startup pulses ? shutdown ir3823 can be shut down by pulling the enable pin below its 1.0v threshold. both the high side and the low side drivers will be pulled low. operating frequency the switching frequency can be programmed between 300khz ? 1200khz by connecting an external resistor from rt pin to gnd. rt can be calculated as follows. 953 . 0 19954 ? ? ? t s r f where f s is in khz, and rt is in k ? . table 3 shows the different oscillator frequency and its corresponding rt for easy reference. table 3 switching frequency vs. r t r t (k ? ) f s (khz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 over current protection the over current (oc) prot ection is performed by sensing current through the r ds(on) of the synchronous mosfet. this method enhances the converter?s efficiency, redu ces cost by eliminating a current sense resistor and any layout related noise issues. the current limit is pre-set internally and is compensated according to the ic temperature. so at different ambient temperature, the over-current trip threshold remains almost constant. detailed operation of ocp is explained as follows. over current protection circuit senses the inductor current flowing through the synchronous mosfet closer to the valley point. ocp circuit samples this current for 40nsec typically after the rising edge of the pwm set pulse, which has a width of 12.5% of the switching period. the pwm pulse starts at the falling edge of the pwm set pulse. this makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. an oc condition is detected if the load current exceeds the threshold, the converter enters ir3823 21 www.irf.com ? 2012 international rectifier august 1, 2013 into hiccup mode. pgood will go low and the internal soft start signal will be pulled low. the converter goes into hiccup mode with some hiccup blanking time as shown in figure 16. the convertor stays in this mode until the over load or short circuit is removed. with different ss_select configurations, the hiccup blanking time is different. please refer to the electrical table for details. the actual dc output current limit point will be greater than the valley point by an amount equal to approximately half of peak to peak inductor ripple current. 2 i i i limit ocp ? ? ? i ocp = dc current limit hiccup point i limit = over current limit (va lley of inductor current) ? i= peak-to-peak inductor ripple current figure 16: timing diagram for hiccup ocp over current limit is affected by the v cc voltage. for some single rail operations where v in is 5v or less, the ocp limit will de-rated due to the drop of v cc voltage. figure 17 and figure 18 show the over current limit for two single rail applications with v in =pv in =5v and v in =pv in =v cc =4.5v respectively. figure 17:ocp limit at v in =pv in =5v using internal ldo figure 18: ocp limit at v in =pv in =v cc =4.5v over-voltage protection (ovp) over-voltage protection in ir3823 is achieved by comparing fb pin voltage to a pre-set threshold. ovp threshold is set at 1.2vref. when fb pin voltage exceeds the over vo ltage threshold, an over voltage trip signal asserts after 2us (typ.) delay. then the high side drive signal hdrv is turned off immediately, pgood flags low. the sync fet remains on to discharge the output capacitor. when the v fb voltage drops below the threshold, the sync fet turns off to prevent the complete depletion of the output capacitor. after that, hdrv remains off until a reset is performed by cycling either v cc or enable. figure 19 shows the timing diagram for over voltage protection. please note that ovp comparator becomes active only when the ir3823 is enabled. ? figure 19: timing diagram for over voltage protection ir3823 22 www.irf.com ? 2012 international rectifier august 1, 2013 power good output ir3823 continually monitors the output voltage via fb voltage. the fb voltage is an input to the window comparator with upper and lower threshold of 120% and 85% of the reference voltage respectively. pgood signal is high whenever fb voltage is within the pgood comparator window thresholds. for pre- biased start-up, pgood is not active until the first gate signal of the control fet is generated. the pgood pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. in addition, pgood is also gated by other faults including over current and over temperature. when either of the faults occurs, pgood pin will be pulled low. thermal shutdown temperature sensing is provided inside ir3823. the trip threshold is typically set to 145oc. when trip threshold is exceeded, thermal shutdown turns off both mosfets and resets the internal soft start. automatic restart is in itiated when the sensed temperature drops within the operating range. there is a 20c hysteresis in the thermal shutdown threshold. external synchronization ir3823 incorporates an internal phase lock loop (pll) circuit which enables synchronization of the internal oscillator to an external clock. this function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (pol ) regulators are used. a multi-function pin, rt/sync, is used to connect the external clock. if the exter nal clock is present before the converter turns on, rt/sync pin can be connected to the external clock signal solely and no other resistor is needed. if the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal free- running frequency, an external resistor from rt/sync pin to gnd is required to set the free-running frequency. when an external clock is applied to rt/sync pin after the converter runs in steady state with its free- running frequency, a transition from the free-running frequency to the external clock frequency will happen. this transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. on the contrary, when the external clock signal is removed from rt/sync pin, the switching frequency is also changed to free-running gradually. in order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and rt/sync pin, as shown in figure 20. figure 21 shows the timing diagram of these transitions. an internal compensation circuit is used to change the pwm ramp slope according to the clock frequency applied on rt/sync pin. thus, the effective amplitude of the pwm ramp (v ramp ), which is used in compensation loop calculation, has minor impact from the variation of the external synchronization signal. ? figure 20: configuration of external synchronization sw sync ... ... gradually change fs1 fs2 fs1 free running frequency synchronize to the external clock return to free- running freq gradually change ? figure 21: timing diagram for synchronization to the external clock (fs1 ir3823 23 www.irf.com ? 2012 international rectifier august 1, 2013 minimum on time considerations the minimum on time is the shortest amount of time for which ctrl fet may be reliably turned on, and this depends on the internal timing delays. for ir3823, the worst case minimum on-time is specified as 60ns. any design or application using ir3823 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 60ns. this is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. s in out s on f v v f d t ? ? ? in any application that uses ir3823, the following condition must be satisfied: on on t t ? (min) s in out on f v v t ? ? (min) , therefore, (min) on out s in t v f v ? ? the minimum output voltage is limited by the reference voltage and hence v out(min) = 0.6v. therefore, ? ? therefore, at the maximum recommended input voltage 21v and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 476 khz. conversely, for operation at the maximum recommended operating frequency (1.65 mhz) and minimum output voltage (0.6v). the input voltage (pv in ) should not exceed 6v, otherwise pulse skipping will happen. maximum duty ratio a certain off-time is specified for ir3823. this provides an upper limit on the operating duty ratio at any given switching frequency. the off-time remains at a relatively fixed ratio to switching period in low and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which ir3823 can operate. figure 22 shows a plot of the maximum duty ratio vs. the switching frequency. ? figure 22: maximum duty cycle vs. switching frequency. s v t v f v on out s in ? / 10 ns 60 v 6 . 0 (min) (min) ? ? ? ? ir3823 24 www.irf.com ? 2012 international rectifier august 1, 2013 design example ? the following example is a typical application for ir3823. the application circuit is shown in figure 26. pv in = v in = 12v (10%) v o = 1.2v i o = 3a peak-to-peak ripple voltage = 1% of v o ? v o = 4% of v o (for 30% load transient) f s = 1mhz ? external pvin monitor (input uvlo) as explained in the section of enable/external pv in monitor, the input voltage, pv in , can be monitored by connecting the enable pin to pv in through a set of resistor divider. when pv in exceeds the desired voltage level such that the voltage at the enable pin exceeds the enable threshold, 1.2v, the ir3823 is turned on. the implementation of this function is shown in figure 7. for a typical enable threshold of v en = 1.2 v 2 . 1 2 1 2 (min) ? ? ? ? en in v r r r pv en in en v pv v r r ? ? ? (min) 1 2 for the minimum input voltage pv in (min) = 9.2v, select r 1 =49.9k ? , and r 2 =7.5k ? . switching frequency for f s = 1mhz, select rt = 23.2 k ? , from table 3. output voltage setting output voltage is set by the reference voltage and the external voltage divider connected to the fb pin. the fb pin is the inverting input of the error amplifier, which is internally referenced to 0.6v. the divider ratio is set to provide 0.6v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: ) 1 ( 2 1 f f ref o r r v v ? ? ? ? r f1 and r f2 are the feedback resistor divider, as shown in figure 23 . ? for the selection of r f1 and r f2 , please see feedback compensation section. ? ? figure 23: the output voltage is programmed through a set of feedback resistor divider bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected to the source of the control fet. this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor, c1, as shown in figure 24. the operation of the circuit is as follows: when the sync fet is turned on, the capacitor node connected to sw is pulled low. v cc starts to charge c1 through the internal bootstrap didoe. the voltage, v c , across the bootstrap capacitor c1 can be calculated as d cc c v v v ? ? ? where v d is the forward voltage drop of the bootstrap diode. when the control fet turns on in the next cycle, the sw node voltage rises to the bus voltage, pv in . the voltage at the boot pin becomes: ? d cc in boot v v pv v ? ? ? ? ir3823 25 www.irf.com ? 2012 international rectifier august 1, 2013 a good quality ceramic capacitor of 0.1 f with voltage rating of at least 25v is recommended for most applications. ? figure 24: bootstrap circuit to generate the supply voltage for the high-side driver voltage input capacitor selection good quality input capacitors are necessary to minimize the input ripple voltage and to supply the switch current during the on-time. the input capacitors should be selected based on the rms value of the input ripple current and requirement of the input ripple voltage. the rms value of the input ripple current can be calculated as follows: ) 1 ( d d i i o rms ? ? ? ? where d is the duty cycle and i o is the output current. for i o =6a and d=0.1, i rms = 0.9a the input voltage ripple is t he result of the charging of the input capacitors and the voltage induced by esr and esl of the input capacitors. ceramic capacitors are recommended due to their high ripple current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is suggested to use two 10 f/25v ceramic capacitors, c3216x5r1e106m, from tdk. in addition, although not mandatory, a 1x100uf, 25v smd capacitor eee-1ea101xp from panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. inductor selection the inductor is selected based on output power, operating frequency and effi ciency requirements. a low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ? i). the optimum point is usually found between 20% and 50% ripple of the output current. the saturation current of the inductor is desired to be higher than the over current limit plus the inductor ripple current. an inducto r with soft-saturation characteristic is recommended. for the buck converter, t he inductor value for the desired operating ripple current can be determined using the following relation: t i l v pv l o in ? ? ? ? ? max max ; s f d t ? ? s l in o o in f i v v v pv l ? ? ? ? ? ? max max ) ( where: pv inmax = maximum input voltage v 0 = output voltage ? i lmax = maximum inductor peak-to-peak ripple current f s = switching frequency ? t = on time d = duty cycle ? ? select ? i lmax 36%i o , then the output inductor is calculated to be 1.0 h. select l=1.0 h, xfl4020- 102me, from coilcraft which provides a compact, low profile inductor suitable for this application. output capacitor selection output capacitors are usually selected to meet two specific requirements: (1 ) output ripple voltage and ir3823 26 www.irf.com ? 2012 international rectifier august 1, 2013 (2) load transient response. the load transient response is also greatly affected by the control bandwidth. so it is common practice to select the output capacitors to meet the requirements of the output ripple voltage first, and then design the control bandwidth to meet the transient load response. for some cases, even with the highest allowable control bandwidth, the resulting load transient response still can not meet the requirement. the number of output capacitors then need to be increased. the voltage ripple is attributed by the ripple current charging the output capacitors, and the voltage drop due to the equivalent series resistance (esr) and the equivalent series inductance (esl). following lists the respective peak-to-peak ripple voltages: esl l v pv v esr i v f c i v o in esl o l esr o s o l c o ? ? ? ? ? ? ? ? ? ? ? ? ? ) ( 8 ) ( max ) ( max ) ( ? where ? i lmax is maximum inductor peak-to-peak ripple current. good quality ceramic capacitors are recommended due to their low esr, esl and the small package size. it should be noted that the capacitance of ceramic capacitors are usually de-rated with the dc and ac biased voltage. it is important to use the de- rated capacitance value for the calculation of output ripple voltage as well as the voltage loop compensation design. the de-rated capacitance value may be obtained from the manufacturer?s datasheets. in this case, one 22uf ceramic capacitors, c2012x5r0j226m, from tdk are used to achieve 12mv peak-to-peak ripple voltage requirement. the de-rated capacitance value with 1.2vdc bias and 10mvac voltage is around 18uf each. feedback compensation for this design, the resonant frequency of the output lc filter, f lc , is khz 5 . 37 10 18 1 10 0 . 1 2 1 2 1 6 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? o o lc c l f the equivalent esr zero of the output capacitors, f esr , is. khz 10 9 . 2 10 18 10 3 2 1 1 2 1 3 6 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o esr c esr f designing crossover frequency at 1/5 th of switching frequency gives f 0 =200 khz. according to table 1, ty pe iii b compensation is selected for f lc ir3823 28 www.irf.com ? 2012 international rectifier july 18, 2013 application diagram figure 26: single rail 3a pol application circuit: pv in =v in =12v, v o =1.2v, io=3a, f sw =1mhz suggested bill of materials qty part reference value description manufacturer part number 2 c in 10uf 1206, 25v, x5r, 20% tdk c3216x5r1e106m 3 c7, c12, c24 0.1uf 0603, 25v, x7r, 10% murata grm188r71e104ka01b 1 c11 56pf 0603, 50v, np0, 5% tdk c1608c0g1h560j080aa 1 c out 22uf 0805, 6.3v, x5r, 20% tdk c2012x5r0j226m 1 c8 2200pf 0603,50v,x7r murata grm188r71h222ka01b 1 c23 2.2uf 0603, 16v, x5r, 20% tdk c1608x5r1c225m 1 c26 4700pf 0603, 50v 10% x7r murata grm188r71h472ka01d 1 c32 1.0uf 0603, 25v, x5r, 10% murata grm188r61e105ka12d 1 r1 1.0k thick film, 0603,1/10w,1% panasonic erj-3ekf1001v 2 r2, r3 4.02k thick film, 0603,1/10w,1% panasonic erj-3ekf4021v 1 r4 127 thick film, 0603,1/10w,1% panasonic erj-3ekf1270v 1 r9 23.2k thick film, 0603,1/10w panasonic erj-3ekf2322v 2 r17, r18 49.9k thick film, 0603,1/10w,1% panasonic erj-3ekf4992v 1 r19 7.5k thick film, 0603,1/10w,1% panasonic erj-3ekf7501v 1 l 1.0uh smd, 4.0mmx4.0mmx2.1mm, 10.8m ? coilcraft XFL4020-102ME 1 u1 ir3823 3a pol, pqfn 3.5mm x3.5mm ir ir3823 ir3823 29 www.irf.com ? 2012 international rectifier july 18, 2013 application diagram boot vcc/ldo_out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3823 ss_select 12v pgood 1.2v 1.0uf 2x10uf c in c 32 49.9k r 18 7.5k r 19 49.9k r 17 2.2uf c 23 23.2k r 9 0.1uf c 24 0.1uf c 7 l 1 1.0uh 4.02k r 2 127 ?? r 4 4.02k r 3 475 ?? r 1 c 26 15nf c 11 220pf c 8 2200pf cout 22uf c 12 0.1uf ext ? vcc=5v figure 27: 3a pol application circuit with external 5v v cc : pv in =v in =12v, v o =1.2v, io=3a, f sw =1mhz. please note that loop compensation is adjusted to consider the absence of the input voltage feedforward. boot vcc/ldo_out fb comp gnd pgnd sw pgood rt/sync pvin vin enable ir3823 ss_select 5v pgood 1v 1.0uf 3x10uf c in c 32 enable 49.9k r 17 2.2uf c 23 23.2k r 9 0.1uf c 24 0.1uf c 7 l 1 1.0uh 4.02k r 2 127 ?? r 4 6.04k r 3 1k r 1 c 26 4.7nf c 11 100pf c 8 2200pf cout 22uf c 12 0.1uf figure 28: single rail 3a pol application circuit: pv in =v in =5v, v o =1.0v, io=3a, f sw =1mhz ir3823 30 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating waveforms v in = 12v, v 0 = 1.2v, i 0 = 0-3a, unless otherwise specified, ss_sele ct = float. room temperature, no air flow figure 29: start up at 3a load with ss_select pin figure 30: start up at 3a load with ss_select pin floating. ch 1 :v in , ch 2 : p good , ch 3 :v o ,ch 4 : enable floating. ch 1 :v in , ch 2 : v cc , ch 3 :v o ,ch 4 : enable figure 31: start up with 1.06v pre bias, 0a load figure 32: output voltage ripple, 3a load ch 3 : v out ch 3 :v o , ch 2 :p good figure 33: inductor node at 3a load, ch3: sw node figure 34: short ci rcuit (hiccup) recovery, ch3:vout , ch4:iout ir3823 31 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating waveforms v in = 12v, v 0 = 1.2v, i 0 = 0-3a, unless otherwise specified, ss_sele ct = float. room temperature, no air flow figure 35: transient response, 2a to 3a figure 36: feed forward for v in change step load ch 3 :v out ch4-i out from 7 to 14v and back to 7v. ch 3 -v out , ch 4 -v in figure 37: bode plot at 6a load, bandwidth = 188 khz, and phase margin = 53 degrees and gain margin = -10db ir3823 32 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating waveforms v in = 12v, v 0 = 1.2v, i 0 = 0-3a, unless otherwise specified, ss_sele ct = float. room temperature, no air flow figure 38: efficiency vs. load current figure 39: power loss vs. load current ir3823 33 www.irf.com ? 2012 international rectifier august 1, 2013 typical operating waveforms v in = 12v, v 0 = 1.2v, i 0 = 0-3a, unless otherwise specified, ss_sele ct = float. room temperature, no air flow figure 40: thermal image of the board at 3a load, ir3823=45c, inductor=41.3c ir3823 34 www.irf.com ? 2012 international rectifier august 1, 2013 layout recommendations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with worse than expected results. make the connections for the power components in the top layer with wide, copper fille d areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, output capacitors and the ir3823 should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the pv in pin of ir3823. the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass components such as capacitors for v in and v cc should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. it is recommended to place all the compensation parts over the analog ground plane in top layer. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 4-layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using via holes. figure 41-figure 44 illustrates the implementation of the layout guidelines outlined above, on the irdc3823 4-layer demo board. figure 41: irdc3823 de mo board ? top layer pv in pgnd agnd vout compensation parts should be placed as close as possible to the comp pin ? ? ? resistor rt should be placed as close as possible to their pins a llow enough copper & minimum ground length path between input and output ? ? ? ? sw node copper is kept only at the top layer to minimize the switching noise a ll bypass caps should be placed as close as possible to their connecting pins ? single point connection between agnd & pgnd, should be close to the supirbuck and kept away from noise ir3823 35 www.irf.com ? 2012 international rectifier august 1, 2013 figure 42: irdc3823 demo board ? bottom layer figure 43: irdc3823 demo board ? middle layer 1 pv in pgnd vout agnd pgnd ir3823 36 www.irf.com ? 2012 international rectifier august 1, 2013 figure 44: irdc3827 demo board ? middle layer 2 feedback and vsns trace routing should be kept away from noise sources pgnd ir3823 37 www.irf.com ? 2012 international rectifier august 1, 2013 pcb metal an d component placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. for further information, please refer to ?supirbuck ? ? multi-chip module (mcm) power quad flat no-lead (pqfn) board mounting application note.? (an1132) figure 45: pcb metal pad spacing (all dimensions in mm) * contact international rectifier to receive an elec tronic pcb library file in your preferred format ir3823 38 www.irf.com ? 2012 international rectifier august 1, 2013 solder resist ir recommends that the larger power or land area pads are solder mask defined (smd.) this allows the underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. when using smd pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the solder mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in x & y.) however, for the smaller signal type leads around the edge of the device, ir recommends that these are non solder mask defined (nsmd) or copper defined. when using nsmd pads, the solder resist window should be larger than the copper pad by at least 0.025mm on each edge, (i.e. 0.05mm in x&y,) in order to accommodate any layer to layer misalignment. ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. figure 46: solder resist ir3823 39 www.irf.com ? 2012 international rectifier august 1, 2013 stencil design stencils for pqfn can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. this design is for a stencil thickness of 0.127mm (0.005"). the reduction should be adjusted for stencils of other thicknesses. figure 47: stencil pad spacing (all dimensions in mm) ir3823 40 www.irf.com ? 2012 international rectifier august 1, 2013 marking information package information ir3823 41 www.irf.com ? 2012 international rectifier august 1, 2013 environmental qualifications ? qualification level industrial moisture sensitivity level 3.5mm x 3.5mm pqfn jedec level 2 @ 260c esd machine model (jesd22-a115a) class b ? 200v to <400v human body model (jesd22-a114f) class 2 ? 2000v to <4000v charged device model (jesd22-c101d) class iii ? 500v to 1000v rohs6 compliant yes ? qualification standards can be found at inter national rectifier web site: http://www.irf.com ?? exceptions to aec-q101 requirements are noted in the qualification report. ? data ? and ? specifications ? subject ? to ? change ? without ? notice. ? qualification ? standards ? can ? be ? found ? on ? ir?s ? web ? site. ? ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com |
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